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| 24C02 / 24C04 / 24C08 / 24C16 Features Wide Voltage Operation Operating Ambient Temperature: -40 C to +85 C Internally Organized: - 24C02, 256 X 8 (2K bits) - 24C04, 512 X 8 (4K bits) - 24C08, 1024 X 8 (8K bits) - 24C16, 2048 X 8 (16K bits) - VCC = 1.8V to 5.5V 1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility Write Protect Pin for Hardware Data Protection 8-byte Page (2K), 16-byte Page (4K, 8K, 16K) Write Modes Partial Page Writes Allowed Self-timed Write Cycle (5 ms max) High-reliability - Endurance: 1 Million Write Cycles - Data Retention: 100 Years Two-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol General Description The 8-lead PDIP, 8-lead SOP and 8-lead TSSOP Packages Die Sales: Wafer Form, Waffle Pack 24C02/ 24C04/ 24C08/ 24C16 provides 2048/4096/8192/16384 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 256/512/1024/2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The 24C02/ 24C04/ 24C08/ 24C16 is available in space-saving 8-lead PDIP, 8-lead SOP, and 8-lead TSSOP packages and is accessed via a two-wire serial interface. Pin Configuration 8-lead PDIP C16 / C08 / C04 / C02 NC / NC / NC / A0 NC / NC / A1 / A1 NC / A2 / A2 / A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA C16 / C08 / C04 / C02 NC / NC / NC / A0 NC / NC / A1 / A1 NC / A2 / A2 / A2 GND 8-lead SOP 1 2 3 4 8 7 6 5 VCC WP SCL SDA 8-lead TSSOP C16 / C08 / C04 / C02 NC / NC / NC / A0 NC / NC / A1 / A1 NC / A2 / A2 / A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA Pin Descriptions Table 1: Pin Configuration Pin Designation Type Name and Functions A0 - A2 SDA SCL WP GND VCC NC I Address Inputs Serial Data Serial Clock Input Write Protect Ground Power Supply No Connect I/O & Open-drain I I P P NC BEIJING ESTEK ELECTRONICS CO.,LTD 1 24C02 / 24C04 / 24C08 / 24C16 Block Diagram VCC GND WP SCL SDA START STOP LOGIC EN SERIAL CONTROL LOGIC LOAD COMP DEVICE ADDRESS COMPARATOR HIGH VOLTAGE PUMP/TIMING DATA RECOVERY C16 / C08 / C04 / C02 NC / NC / NC / A0 NC / NC / A1 / A1 NC / A2 / A2 / A2 DATA WORD ADDRESS COUNTER LOAD INC X DECODER EEPROM Y DECODER SERIAL MUX DIN DOUT/ACKNOWLEDGE DOUT BEIJING ESTEK ELECTRONICS CO.,LTD 2 24C02 / 24C04 / 24C08 / 24C16 Pin Descriptions DEVICE/PAGE ADDRESSES (A2, A1 and A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the The The The 24C02. Eight 2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). 24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a 24C08 only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a single 24C16 does not use the device address pins, which limits the number of devices on a single bus to one. The A0, single bus system. The A0 pin is a no connect and can be connected to ground. bus system. The A0 and A1 pins are no connects and can be connected to ground. A1 and A2 pins are no connects and can be connected to ground. SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open- collector devices. SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. WRITE PROTECT (WP): The 24C02/ 24C04/ 24C08/ 24C16 has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is connected to VCC, the write protection feature is enabled and operates as shown in the following Table 2. Table 2: Write Protect WP Pin Status Part of the Array Protected 24C02 Full (2K) Array 24C04 Full (4K) Array 24C08 Full (8K) Array 24C16 Full (16K) Array At VCC At GND Normal Read / Write Operations Memory Organization 24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit data word address for random word addressing. 24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit data word address for random word addressing. 24C08, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data word address for random word addressing. 24C16, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit data word address for random word addressing. BEIJING ESTEK ELECTRONICS CO.,LTD 3 24C02 / 24C04 / 24C08 / 24C16 Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see to Figure 1 on page 4). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see to Figure 2 on page 4). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 2 on page 4). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The 24C02/ 24C04/ 24C08/ 24C16 features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: 1. 2. 3. Clock up to 9 cycles. Look for SDA high in each cycle while SCL is high. Create a start condition. Figure 1: Data Validity SDA SCL DATA STABLE DATA CHANGE DATA STABLE Figure 2: Start and Stop Definition SDA SCL START STOP BEIJING ESTEK ELECTRONICS CO.,LTD 4 24C02 / 24C04 / 24C08 / 24C16 Figure 3: Output Acknowledge SCL 1 8 9 DATA IN DATA OUT START ACKNOWLEDGE Device Addressing The 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see to Figure 4 on page 7). The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. This is common to all the Serial EEPROM devices. The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3 bits must compare to their corresponding hardwired input pins. The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corresponding hardwired input pins. The A0 pin is no connect. The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect. The 16K does not use any device address bits but instead the 3 bits are used for memory page addressing. These page addressing bits on the 4K, 8K and 16K devices should be considered the most significant bits of the data word address which follows. The A0, A1 and A2 pins are no connect. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return to a standby state. BEIJING ESTEK ELECTRONICS CO.,LTD 5 24C02 / 24C04 / 24C08 / 24C16 Write Operations BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in the first 8bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 5 on page 7). PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and 16K devices are capable of 16-byte page writes. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a "0" after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 6 on page 7). The data word address lower three (2K) or four (4K, 8K, 16K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (2K) or sixteen (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word address will "roll over" and previous data will be overwritten. ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a "0", allowing the read or write sequence to continue. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to "1". There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input "0" but does generate a following stop condition (see Figure 7 on page 8). BEIJING ESTEK ELECTRONICS CO.,LTD 6 24C02 / 24C04 / 24C08 / 24C16 Read Operations RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 8 on page 8). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 9 on page 8). Figure 4: Device Address 2K 4K 8K 16K 1 MSB 1 1 1 0 0 0 1 1 1 0 0 0 A2 A2 P2 A1 P1 P1 P0 P0 P0 0 1 0 A2 A1 A0 R/W LSB R/W R/W R/W Figure 5: Byte Write S T A R DEVICE T ADDRESS SDA LINE M S B L R AM S / CS BWK B LA SC BK A C K W R I T E WORD ADDRESS DATA S T O P Figure 6: Page Write S W T R A I R DEVICE T ADDRESS E T SDA LINE M S B L R AM S / CS BWK B LA SC BK A C K A C K A C K WORD ADDRESS(n) DATA( n ) DATA( n+1 ) DATA( n+x ) S T O P BEIJING ESTEK ELECTRONICS CO.,LTD 7 24C02 / 24C04 / 24C08 / 24C16 Figure 7: Current Address Read S T A R DEVICE T ADDRESS SDA LINE M S B L RA S/C BWK N O A C K R E A D S T O P DATA Figure 8: Random Read W S R T I A DEVICE T R T ADDRESS E SDA LINE M S B L R AM S / CS BWK B LA M SC S BK B LRA S/C BWK N O A C K WORD ADDRESS(n) S T A R DEVICE T ADDRESS R E A D S T O P DATA( n ) DUMMY WRITE Figure 9: Sequential Read R E DEVICE A ADDRESS D SDA LINE RA /C WK A C K A C K A C K N O A C K S T O DATA( n+x ) P DATA( n ) DATA( n+1 ) DATA( n+2 ) BEIJING ESTEK ELECTRONICS CO.,LTD 8 24C02 / 24C04 / 24C08 / 24C16 Electrical Characteristics Absolute Maximum Stress Ratings DC Supply Voltage . . . . . . . . . . . . . . . . .-0.3V to +6.5V Input / Output Voltage . . . . . . . .GND-0.3V to VCC+0.3V Operating Ambient Temperature . . . . . -40 C to +85 C Storage Temperature . . . . . . . . . . . . -65 C to +150 C Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics Applicable over recommended operating range from: TA = -40 C to +85 C, VCC = +1.8V to +5.5V (unless otherwise noted) Parameter Symbol Min. Typ. Max. Unit Condition Supply Voltage Supply Current VCC = 5.0V Supply Current VCC = 5.0V Standby Current Input Leakage Current Output Leakage Current Input Low Level Input High Level Output Low Level VCC =5.0V Output Low Level VCC =3.0V Output Low Level VCC =1.8V VCC ICC1 ICC2 ISB ILI ILO VIL VIH VOL3 VOL2 VOL1 1.8 -0.6 VCC X 0.7 - 0.4 2.0 0.05 - 5.5 1.0 3.0 1.0 3.0 3.0 VCC X 0.3 VCC + 0.5 0.4 0.4 0.2 V mA mA A A A V V V V V IOL = 3.0 mA IOL = 2.1 mA IOL = 0.15 mA READ at 100 kHz WRITE at 100 kHz VIN = VCC or GND VIN = VCC or GND VOUT = VCC or GND Pin Capacitance Applicable over recommended operating range from TA = 25 C, f = 1.0 MHz, VCC = +1.8V Parameter Symbol Min. Typ. Max. Unit Condition Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL) CI/O CIN - - 8 6 pF pF VI/O = 0V VIN = 0V BEIJING ESTEK ELECTRONICS CO.,LTD 9 24C02 / 24C04 / 24C08 / 24C16 AC Electrical Characteristics Applicable over recommended operating range from TA = -40 C to +85 C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted) Parameter Symbol 1.8-volt Min. Typ. Max. Min. 5.0-volt Typ. Max. Units Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Noise Suppression Time Clock Low to Data Out Valid Time the bus must be free before a new transmission can start Start Hold Time Start Setup Time Data In Hold Time Data In Setup Time Inputs Rise Time(1) Inputs Fall Time(1) Stop Setup Time Data Out Hold Time Write Cycle Time 5.0V, 25 C, Byte Mode fSCL tLOW tHIGH tI tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR Endurance 1.2 0.6 0.05 1.2 0.6 0.6 0 100 0.6 50 1M - 400 50 0.9 0.3 300 5 - 0.6 0.4 0.05 0.5 0.25 0.25 0 100 0.25 50 - - 1000 40 0.55 0.3 100 5 - kHz s s s s s s s s ns s ns s ns ms Write Cycles Note 1. This parameter is characterized and is not 100% tested. 2. AC measurement conditions: RL (connects to VCC): 1.3 k Input rise and fall time: (2.5V, 5V), 10 k (1.8V) Input pulse voltages: 0.3 VCC to 0.7 VCC 50 ns Input and output timing reference voltages: 0.5 VCC The value of RL should be concerned according to the actual loading on the user's system. BEIJING ESTEK ELECTRONICS CO.,LTD 10 24C02 / 24C04 / 24C08 / 24C16 Bus Timing Figure 10: SCL: Serial Clock, SDA: Serial Data I/O tF tLOW SCL tSU.STA tHD.STA tHD.DAT tSU.DAT tSU.STO tHIGH tLOW tR SDA_IN tAA tDH tBUF SDA_OUT Write Cycle Timing Figure 11: SCL: Serial Clock, SDA: Serial Data I/O SCL SDA 8th BIT ACK tWR(1) STOP CONDITION START CONDITION Note 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. BEIJING ESTEK ELECTRONICS CO.,LTD 11 24C02 / 24C04 / 24C08 / 24C16 Ordering Information Code Number Part Number K 1 1.Prefix 2.Series Name 24: Two-wire (I2C) Interface 3.EEPROM Density C02=2K bits C04=4K bits C08=8K bits C16=16K bits 24 2 XXX 3 X 4 - X 5 X 6 X 7 X 8 - X 9 8.Plating Technology Blank = Standard SnPb plating G = ECOPACK(RoHS compliant) 9.Operating Voltage S=2.7~5.5 A=1.8~5.5 4.Design Option o= (Blank) 5.Package Type D = DIP S = SOP R = TSSOP W = Wafer/die 6. Temperature Range C = Com Temp(0 C-70 C) E = Exp Temp(-40 C-125 C) 7.Pack Type T = Tube R = Tape & Reel I = Ind Temp(-40 C-85 C) Product Datasheet Change Notice Datasheet Revision History Version Content Date 1.0 Datasheet Jan., 2007 BEIJING ESTEK ELECTRONICS CO.,LTD 12 24C02 / 24C04 / 24C08 / 24C16 Disclaimers The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. HHIE assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. HHIE reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of HHIE or others. HHIE makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does HHIE assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. " Typ. " parameters can and do vary in different applications. All operating parameters, including " Typ. " must be validated for each customer application by the customer's technical experts. HHIE products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the HHIE product could create a situation where personal injury or death may occur. Should the Buyer purchase or use a HHIE product for any such unintended or unauthorized application, the Buyer shall indemnify and hold HHIE and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that HHIE was negligent regarding the design or manufacture of said product. 24C Series (I2C Bus) Serial EEPROM Data Sheet, Revision 1.0 2007 HHIE All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of HHIE. BEIJING ESTEK ELECTRONICS CO.,LTD 13 |
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